In common forms of an image sensor, a two-dimensional array of pixels is read out row by row, the pixels of each column sharing column readout circuitry which commonly comprises correlated double sampling and ADC.
In European Patent Application EP1956715A, the disclosure of which is hereby incorporated by reference, there is disclosed an ADC arrangement for an image sensor, one embodiment of which is shown in FIG. 1 of the present application, and described later.
Although this prior arrangement provides advantages over the prior art, it has been found to have some deficiencies when applied to large arrays and/or high speeds. This is because the ramping signal used in the analog to digital conversion of the pixel level suffers from a slight delay before it actually begins ramping. The delay affects column capacitors differently across the x-direction of the array, causing an effect in the resulting image sometimes referred to as “x-droop”.
There is a need in the art to address this issue.